Hi Ramnath,
Looking at the screenshots it appears the TPS40170 entering current limit hiccup mode. Most likely it is falsely triggering the SCP. To remove this issue the use of a snubber and series resistor to slow down the turn on the high-side FETs is recommended. The snubber is dependent on layout but the following link gives a good step by step process: http://www.ti.com/ww/en/analog/power_management/snubber_circuit_design.html. For the series resistors a 4.7 ohm is a typical value used in series with the high-side gate drive signal and with the bootstrap capacitor. Lastly I recommend trying to replace R23 with a 1Ω resistor. The voltage drop from the bias current has been known to falsely trip SCP if the resistance is too high.
There are also some layout improvements which could help remove the issue. With higher input voltages this is important because the switching node will be changing from GND to the input voltage. It is most important to minimize the input current loop which is marked up in yellow in the image in the following link: http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/196/0121.High-current-loop-EVM.png. I could only find C38 on the layout and this is relatively far from the high-side and low-side FETs.
I also noticed there are only 2x 10uF for the input capacitor. Is there some bulk capacitance elsewhere on the board? This seems small.
Best Regards,
Anthony