Shortly after power is applied and the reference of UCC28950 is established (~4mSec), output drive waveforms on A, B,C,and D are produced that are unexpected, based on the specified operation of the chip. They last for approximately two switching cycle periods. Though their phasing would normally represent a zero power transfer, no active high outputs are expected until the SS/EN pin is released. Both this SS/EN pin and the EA+ pins are clamped to ground during this period. The only other dynamic pin change, noted at the time of the unexpected output drive, is an alteration in the RT signal, which falls momentarily from Vref to ground before settling at Vref/2, due to internal IC influences alone.
Your forum GUI does not appear to accept bmp or png images, or a pdf attachment with these images included, at this time. I trust that the description alone is sufficient.