Hi.
Here are another two doubts.
1)
When IC1 (TPS54240) is generating the 5V rail, there will be 5V at VOUT pin of IC3 (TPS63020).
Under this situation, what happens if ENABLE pin of IC3 (TPS63020) is pulled to logic LOW and also, if EN = '1' and IC3 is in shutdown mode due to VIN undervoltage. There will be connection between VIN and VOUT? Or there will be just a little leakage current from VOUT to VIN pin? Both transistors, Q3 and Q4, shown in the diagram below, will stay in OFF?
2)
When IC3 (TPS62030) is generating the 5V rail, there will be 5V at PH pin of IC1 (TPS54240).
Considering EN pin of TPS54240 is logic '0', there will be connection between PH and VIN pins? Or just a little leakage current?
