Hi Sonoki,
The resistor in question (R4 in the schematic) is there to limit the current from the SW pin. Many devices are the same in this respect, that all pins are at voltages of zero or higher. Everything is above or at ground, including everything inside the device. But the SW node (drain of LS FET and source of HS FET) will fall below zero during the two dead times, which is just before and just after a high-side pulse. The dead time just before a HS pulse is less of an issue because there is almost no delta V. But the dead time just after a HS pulse often has much more noise and activity because the delta V is high as it just dropped from Vin.
This noise can swing significantly below ground, even quite a bit beyond the body diode voltage of the low side FET, depending on many factors including dv/dt, the FET characteristics, and it is also very layout dependent.
On any device like the TPS40195, if a pin gets pulled below ground by more than a diode drop, this voltage can induce currents in parasitic internal P-N junctions. These junctions are not deliberate transistors or diodes, but they arise from the proximity of adjacent P and N materials from two unrelated deliberate devices. This parasitic current (or substrate current) can flow into sensitive nodes and result in corruption of that node, and can result in affecting the operation of the controller in an unwanted manner. The effect could be any of many things, including increased jitter, regulation, and even logic thresholds. This phenomenon is not specific to the TPS40195 or TPS40060, but any device that has one of its pins pulled below the substrate voltage, and it is not specific to 40K devices, and not specific to just TI devices. However, some devices have an internal resistor to perform the same function.
The effect on controller operation will depend on many things, including the controller itself. In the 40060, the parasitic substrate current was seen to be more of an issue at low input voltages, but that does not necessarily mean the same for the 40195 or others. It is device (and dv/dt, FET, and layout) dependent.
So this resistor is to limit the induced currents that can arise from the SW pin being pulled below zero.
Regards,
MC.
