I still need to verify that the suggested capacitive coupling will really work properly. From the "simplified sync circuit" in the datasheet, it seems that the chip will hold the sync pin low for some time after it initially goes low. If the chip is still holding the pin low when the sync signal goes high, that will charge the capacitor and make it impossible for the rising edge to register when the chip stops holding the sync pin low. Unfortunately it doesn't seem possible to determine what will really happen from the simplified diagram of the chip.
I have a very noise sensitive environment, and I need to have high confidence that the sync scheme will work properly, with no glitches. The power supply will be in the inverting configuration, so the ground reference for the chip will be at -9V relative to my system (and sync) ground. The sync signal will be 3.3V CMOS at 700 kHz.
Can you provide further guidance?
Thanks!