First check your differential voltage level at the SENSE pins to be sure it is what you expect. The part detects the voltage at the pins, not the actual current. It can be difficult to get a good sense point with multiple parallel resistors.
Second, consider your SCD protections. If you are using the minimum 60us setting, be aware the part samples the input with a clock for timing and at the minimum delay, it must act on a single sample above the threshold to achieve this short delay. A longer SCDD time will allow multiple samples. Look at the differential SENSE voltage with a high resolution, high sample rate scope to determine if you have a threshold crossing. Also look for noise coupling on ZEDE. The datasheet recommends a strong pulldown to VSS. Noise on the ZEDE can cause minimum delay and make the part respond to a single SCD/OCD sample
Third, determine if you are getting a protection event or a reset, or a reset after a protection event. Check to see if VREG is still present after the event. Since you indicate CHGCTL (CHGST) must be brought high to turn on FETs again, it would seem the part may be off. See http://www.ti.com/lit/slua612 for a description of some events which can cause shutdown or problems. Check your ground placement. Ground noise can cause reset of the device. Look for noise coupling between the current path and ground traces.