Hi Adam,
Sorry for the confusion. You are right that the pull-up current from BP to EN/SS with the existence of FSS resistor will lead to shorter soft-start time. When the input voltage is above 6.5V, the soft-start time will be cut short to ~1/3 of the calculated value. When the input voltage is 4V, the soft-start time will be cut short to ~1/2 of the calculated value.
You are also right about the high-side and low-side current sensing. The high-side sensing is based on VDD-SW voltage and low-side sensing is based on SW-GND. So the VDD should be as close to the drain voltage of high-side FET as possible for better current sensing accuracy.
Regards,
Na