Hello Gioacchino,
I am not the author of the appnote you mentioned, but I will comment on this anyway :)
The portion of the circuit with high di/dt will be from the PGND to the negative terminal of the input capacitor. This section will see pulsing current during each switching cycle. The location of this on the board is approximately the red path below:
The AGND connects to the lower end of the center pad and is not on the way of the high di/dt current, but I agree that it is not too far away either. Also the di/dt current has to go to the bottom layer to return to the input capacitor, which will "pollute" the ground plane on the bottom layer.
I think an improved version of this layout would be if the input capacitor is placed on the "north" side of the IC. Something like this:
The components that were on the north side can go somewhere else. That way the high di/dt current returning from the PGND to the input cap is only on the top layer, the parasitic inductance is lower (smaller loop area!) and the ground plane on the bottom can stay quiet.
Here is an example of how to place the power components along with some downloadable files: http://e2e.ti.com/support/power_management/simple_switcher/w/simple_switcher_wiki/2214.lm5575lm25575-pcb-layout.aspx
In terms of the AGND connection, the example in the link above works well - AGND is connected to the quiet bottom layer through the pad vias and there is no high di/dt current flowing in the bottom ground plane in this case. Another modification/improvement may be to connect the AGND pin directly to the bottom ground layer and not to the pad under the IC. Your idea may also work well, but I have not tried it myself.
I hope this helps.
Regards,
Denislav