1. the 1V threshold on CS is the peak voltage measured from ground reference. You will have a triangular waveform, when the peak hits 1V (typical) the switching cycle will be ended.
2. Is VDD falling low enough to trigger the UVLO off threshold of 9V under any line or load within the normal operating range? If not then I wouldn't redesign the transformer..if it is, you may just try increasing the bulk capacitor on VDD for more holdup time.
3. FB will be relatively stable but have variations as the the control loop compensation reacts to the line and load requirement