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Forum Post: RE: TPS5450DDA exhibits poor step load transient response

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Hi John:

I appologize for the long delay but I had to complete some other work.  Back to the issues with my implemenation of the TPS5450.  I was not vey clear in my past posts.  The test fixture I made had very fast rise and fall times; much faster than I required and I was naive about the implications to the design of the reguator especially since it is internally compensated.  The module is not yet available but I now have some current waveforms from the mfg that indicates it is about 2.5A in 50us or 50mA/us. 

In any case, I modified my test fixture to at least slow down the leading edge of the MOSFET switch and have attached new waveforms in a form more like you requested. 

 

I am now testing with a 1ms, 4A pulse that has a rep rate of 10ms.  The rising edge is now much slower at about 1.5A/us.  Not so bad on the leqading edge but problems on the falling edge (vertical at 200mV/div AC)

 

  

 

but the falling edge is still very fast at about 20A/us

 

 

If I look over a longer time, I see lots of loop instability as it seems to take about 8ms before the output starts to become stable. 

 

 

Given that my target application may require slower a di/dt but needs to be able to handle at least 5A for short durations, do you believe I am ok with TPS5450?   Do you believe the poor transient response on the falling edge is beacuse of the high di/dt or poor matching of the output LC?   Earlier you mentioned lead compensation using a small capacitor across the upper divider resistor.  Will that improve my performance based upon what you see now?    If not, how do I best "tune" my output LC to match the internal compensation?  The data sheet shows that for the voltage mode type 3 compensation networ there are two zeroes at 2170 and 2590 Hz. and a first pole at 2165 Hz with many other poles much higher in frequency.  How do I takle the alignment?  Do I assume the 2165 Hz is the dominant pole and take the average of the two zeroes around 2400Hz.  I asume the output network looks like a series L feeding a shunt comboination of the output C in series with the capacitor ESR.    I can solve for the double pole and single zero but not sure what my goal is?

 

Thanks for your help,

 

Craig


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